Pinned Repositories
CryptoHashAccelerator
Crypto Hash Accelerator
FPGA-SM3-HASH
Description of Chinese SM3 Hash algorithm with Verilog HDL
FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
opentitan
OpenTitan: Open source silicon root of trust
Practical-Cryptography-for-Developers-Book
Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
riscv-isa-extension-for-SM4
RISC-V instruction set extensions for SM4 block cipher
scarv
SCARV: a side-channel hardened RISC-V platform
SM4-SBOX
Verilog Implementation of SM4 s-box
theses
SCARV-related UG, PGR, and PhD thesis archive
raymondrc's Repositories
raymondrc/FPGA-SM3-HASH
Description of Chinese SM3 Hash algorithm with Verilog HDL
raymondrc/FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
raymondrc/SM4-SBOX
Verilog Implementation of SM4 s-box
raymondrc/riscv-isa-extension-for-SM4
RISC-V instruction set extensions for SM4 block cipher
raymondrc/CryptoHashAccelerator
Crypto Hash Accelerator
raymondrc/opentitan
OpenTitan: Open source silicon root of trust
raymondrc/Practical-Cryptography-for-Developers-Book
Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA
raymondrc/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
raymondrc/scarv
SCARV: a side-channel hardened RISC-V platform
raymondrc/theses
SCARV-related UG, PGR, and PhD thesis archive
raymondrc/xcrypto
XCrypto: a cryptographic ISE for RISC-V