Pinned Repositories
40gb_Ethernet_over_QSFP
Ongoing collection of all the code and notes from my 40gb Ethernet master's thesis/project
algo_practice
Cache_Simulator
L1 and L2 Cache Emulator
Chisel_First_Project
First exploratory project for chisel on my github.
Compilers_Final
ECE-483-Branch-Predictor
Simple gshare and bimodal branch predictor terminal emulator and testing tool
FMC424-I2C-Controller
I2C controller to perform required functions to integrate, monitor and utilize FMC424 Dual QSFP+ Vita 57.1 Compliant Mezzanine Board
RiscV_InOrder_Pipelined_CPU
RiscV In-order Pipe-lined Processor that utilizes a completely free and accessible toolchain for testing
RiscV_OoO_Processor
And out of order processor project following the University of Michigan EECS 470 Coursework, from start to finish
System-Verilog-Modules
A collection of various hardware designs and test benches from various projects.
rbride's Repositories
rbride/40gb_Ethernet_over_QSFP
Ongoing collection of all the code and notes from my 40gb Ethernet master's thesis/project
rbride/algo_practice
rbride/Cache_Simulator
L1 and L2 Cache Emulator
rbride/Chisel_First_Project
First exploratory project for chisel on my github.
rbride/Compilers_Final
rbride/ECE-483-Branch-Predictor
Simple gshare and bimodal branch predictor terminal emulator and testing tool
rbride/FMC424-I2C-Controller
I2C controller to perform required functions to integrate, monitor and utilize FMC424 Dual QSFP+ Vita 57.1 Compliant Mezzanine Board
rbride/RiscV_InOrder_Pipelined_CPU
RiscV In-order Pipe-lined Processor that utilizes a completely free and accessible toolchain for testing
rbride/RiscV_OoO_Processor
And out of order processor project following the University of Michigan EECS 470 Coursework, from start to finish
rbride/System-Verilog-Modules
A collection of various hardware designs and test benches from various projects.
rbride/SystemVerilog_Practice_Problems
rbride/Templated-Ordered-Array
A Templated Ordered Array that mimics and order vector for a simple student class
rbride/Verilog-TinyFpga-BX-calculator
The following project is my attempt to create a simply calculator using a 4x4 keybad, a 4 digit 8 segment display, and a TinyFPGA Bx