You can find information on where to drop this in the KiCad documentation.
This design is for:
- 4 layer PCB
- Design constraints for JLCPCB.
- Controlled impedance targeting 50Ω for single-ended and 90Ω for differential.
- JLC04161H-7628 stackup.
- Some general best-practices for net classes, trace, and via dimensions.