handlin seq_statement

[redguardtoo]

See #74 , it's not verilog only problem, any C like language has same issue.
Verilog's begin and end is like { and } in C:

• see https://www.verilog.com/VerilogBNF.html#REF100 for verilog BNG
• see http://lisperator.net/pltut/parser/ for how to write a paser
• let's limit the parser in N (N=5) lines scope from current point

[redguardtoo]

it's done. using some code copied from semantic.