regymm

Post-undergrad amateur programmer

Univ. of Sci. & Tech. of China Forever

Pinned Repositories

osstoolchain-docker-things
Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more
Language:Shell12 0 12
buildroot
buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
Language:Makefile25 5 32
muzy
2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.
19 2 22
PhysicsExp
USTC Physics Experiments Data Processing Tools (大物实验数据处理工具)
Language:Python42 2 26
PYNQSDR
PYNQ-Z1 + AD936X openwifi capable SDR platform
81 9 116
quasiSoC
Linux capable RISC-V SoC designed to be readable and useful.
Language:C133 7 29
SqueakyBoard
My self-designed ZYNQ-7010 4-layer developement board.
Language:TeX29 5 26
termux-reverse-ssh
Make Android phone accessible from a public server, in case of stolen.
Language:Shell36 2 04
USTCcomputer
USTC computer practice code and interesting small projects
Language:Mathematica136
ymmcu-ft2232
FT2232HL JTAG & UART Downloader
14 4 03

regymm's Repositories

regymm/quasiSoC
Linux capable RISC-V SoC designed to be readable and useful.
Language:C133 7 29
regymm/buildroot
buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
Language:Makefile25 5 32
regymm/muzy
2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.
19 2 22
regymm/linux-rv32-quasisoc
Linux kernel 5.18.14 modified to run on 32-bit No-MMU RISC-V systems
Language:C6 2 0
regymm/pcie_7x
PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
Language:Verilog3 1 01
regymm/pComputer
A simple "computer" from scratch, running on FPGA-based hardware.
Language:Verilog3
regymm/plutosdr-fw
PlutoSDR Firmware
Language:Verilog2 2 0
regymm/xvc-pico
Raspberry Pico powered Xilinx Virtual Cable - Xilinx JTAG Cable! This is now quite fast, thanks to tom01h! We also support JTAG + serial terminal over a single cable now. Now with (slow) WiFi support for Pico W!
Language:C2
regymm/bouquet-basic-ngspice
Language:Shell1 0 0
regymm/GenZ
Language:C1
regymm/linux
RV32 Linux for QuasiSoC on FPGA. The default branch works for both MMU/No-MMU
Language:C1 1 01
regymm/MyBlog
My blog on GitHub pages. Based on jekyll. regymm.github.io/MyBlog
Language:HTML1 4 01
regymm/regymm-toy-shop
Everything must go!
Language:SCSS1 2 0
regymm/Time-Card-Flex
PTP grandmaster clock gateware running on the OCP-TAP Time Card and more. Aiming at a fully-open-source infrastructure!
Language:SystemVerilog1
regymm/UberDDR3
Open-sourced DDR3 controller
Language:Verilog1 0 0
regymm/embeddedsw
Xilinx Embedded Software (embeddedsw) Development
Language:HTML
regymm/la32r-Linux
Language:C
regymm/loongson-edu-chiplab
Language:Assembly
regymm/MCUViewer
Real-time embedded variable & trace viewer
regymm/nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
Language:C++
regymm/nextpnr-xilinx-meta
Metadata for the nextpnr-xilinx xc7 flow
regymm/open-la500
Language:Verilog
regymm/pico-dirtyJtag
Language:C
regymm/prjxray
Documenting the Xilinx 7-series bit-stream format.
Language:Python
regymm/prjxray-db
Project X-Ray Database: XC7 Series
regymm/regymm
2 0
regymm/regymm.github.io
My homepage. Have a look!
Language:HTML1 01
regymm/Time-Appliance-Project
Develop an end-to-end hypothetical reference model, network architectures, performance objectives and the methods to distribute, operate, monitor time synchronization within data center and much more...
Language:Tcl0 0
regymm/tt02-verilog-funnyblinky
Funnyblinky for TinyTapeout-02
Language:Verilog2 0
regymm/tt02-verilog-mcpi
Monte Carlo Pi calculator for TinyTapeout-02
Language:Verilog1 0