retospect/tt05-fpna-rs

Minimalistic field programmable neural array

What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Verilog Projects

Edit the info.yaml and uncomment the source_files and top_module properties, and change the value of language to "Verilog". Add your Verilog files to the src folder, and list them in the source_files property.

The GitHub action will automatically build the ASIC files using OpenLane.

How to enable the GitHub actions to build the ASIC files

Please see the instructions for:

• Enabling GitHub Actions
• Enabling GitHub Pages

Resources

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community

What next?

• Submit your design to the next shuttle on the website. The closing date is November 4th.
• Edit this README and explain your design, how it works, and how to test it.
• Share your GDS on your social network of choice, tagging it #tinytapeout and linking Matt's profile:
  • LinkedIn #tinytapeout matt-venn
  • Mastodon #tinytapeout @matthewvenn
  • Twitter #tinytapeout @matthewvenn