richarwood

richarwood's Stars

• alibaba/MNN

  MNN is a blazing fast, lightweight deep learning framework, battle-tested by business-critical use cases in Alibaba. Full multimodal LLM Android App:[MNN-LLM-Android](./apps/Android/MnnLlmChat/README.md)

  Language:C++10.2k1.8k

• Nate711/StanfordDoggoProject

  Stanford Doggo is an open source quadruped robot that jumps, flips, and trots!

  2.4k736

• dpretet/async_fifo

  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

  Language:Verilog32183

• maxs-well/ad7606-driver-verilog

  AD7606 driver verilog

  Language:Verilog3910

• fox6666/VGA-FPGA

  存储器与显示控制器

  Language:VHDL41

• dgschwend/zynqnet

  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

  Language:HTML750295

• m-labs/tdc-core

  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

  Language:Verilog6029

• dawsonjon/FPGA-TX

  FPGA based transmitter

  Language:Verilog9314

• dawsonjon/FPGA-radio

  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC

  Language:VHDL9213

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.5k742

• dawsonjon/Chips-2.0

  FPGA Design Suite based on C to Verilog design flow.

  Language:Python24247

• Xilinx/u-boot-xlnx

  The official Xilinx u-boot repository

  Language:C618799

• iawia002/lux

  👾 Fast and simple video download library and CLI tool written in Go

  Language:Go29k3.1k

• adibis/DDR2_Controller

  DDR2 memory controller written in Verilog

  Language:Verilog7632

• Hsury/AES-Cipher-Chip

  An AES cipher chip supporting 128/256 ECB mode with 8-bit half-duplex data bus, being taped out using SMIC 130nm process.

  Language:Verilog82

• hsharma35/dnnweaver2

  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

  Language:Jupyter Notebook20974

• cellularmitosis/dr-frank-ltz1000

  Dr. Frank's LTZ1000 reference

  Language:Shell83

• maswx/multic

  一个乘以常数的Verilog自动代码生成器

  Language:C51

• freecores/jpegencode

  JPEG Encoder Verilog

  Language:Verilog7534

• danielholanda/LeFlow

  Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

  Language:Verilog607102

• kurikomoe/Daily_1h_ML_learning

  Do from now, at least 1h in one day

  1

• bcattle/hardh264

  A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

  Language:VHDL29167