rimuzhengfan

rimuzhengfan's Stars

• peilin-chen/Zhulong-RISCV-CPU

  CPU Design Based on RISCV ISA

  Language:Verilog6817

• chipsalliance/Cores-VeeR-EL2

  VeeR EL2 Core

  Language:SystemVerilog24373

• Advanced-Microelectronics-Group/OpenC910_Modified

  commit rtl and build cosim env

  Language:SystemVerilog358

• rv2036/rv2036-website

  Official website for Jiachen Project (甲辰计划).

  431

• openhwgroup/cvfpu

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  Language:SystemVerilog414112

• riscvarchive/educational-materials

  Educational materials for RISC-V

  22350

• ForrestBlue/cortexm0ds

  Language:Verilog5031

• vinta/awesome-python

  An opinionated list of awesome Python frameworks, libraries, software and resources.

  Language:Python218k24.8k

• enjoy-digital/litedram

  Small footprint and configurable DRAM core

  Language:Python371119

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k670

• hellovimo/uvm_testbench_gen

  Novel GUI Based UVM Testbench Template Builder

  Language:Python11544

• notable/notable

  The Markdown-based note-taking app that doesn't suck.

  22.5k1.1k

• KasuganoSoraaa/simple-AXI2AHB-bridge

  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

  Language:Verilog3110

• chipsalliance/Cores-VeeR-EH2

  Language:SystemVerilog21056

• google/styleguide

  Style guides for Google-originated open-source projects

  Language:HTML37.2k13.3k

• risclite/SuperScalar-RISCV-CPU

  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

  Language:SystemVerilog19541

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.1k1.1k

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3k745

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.4k1.1k

• microsoft/terminal

  The new Windows Terminal and the original Windows console host, all in the same place!

  Language:C++94.9k8.2k

• pulp-platform/pulp-riscv-gnu-toolchain

  Language:C7051

• efabless/caravel

  Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

  Language:Verilog27865

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1k251

• darwinbeing/EasierUVM

  DOULOS Easier UVM Code Generator

  Language:Perl2514

• oddball/ipxact2systemverilog

  Translates IPXACT XML to synthesizable VHDL or SystemVerilog

  Language:Python5619

• Lampro-Mellon/LM-RISCV-DV

  An Open-Source Design and Verification Environment for RISC-V

  Language:SystemVerilog7326

• pulp-platform/pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

  Language:SystemVerilog436114

• marktext/marktext

  📝A simple and elegant markdown editor, available for Linux, macOS and Windows.

  Language:JavaScript46.3k3.5k

• hdl-util/mipi-csi-2

  Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA

  Language:SystemVerilog6316

• sach/System-Verilog-Packet-Library

  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

  Language:SystemVerilog6824