riscv-non-isa/riscv-arch-test-reports

Hypervisor Extension enable issue

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Our DUT hardware supports H extension, so we want to enable MISA.H = 1.
But Reference-sail_c_simulator doesn't support it at present, which causes some test cases to fail.
How to configure yaml files in this case?

Example in attach files:
Dubhe-90.zip
Dubhe-90_isa.yaml
report.html

Test case fail cause analysis:
1701242605955
In function <Mxcpt_sig_sv> read misa to t1, Our DUT return misa=0x80000000001411AD, which cause branch unsatisfied.
But SAIL always return misa=0x800000000014112D, which doesn't match H extension.