All floating-point instruction tests don't have covergroups

[cmuellner]

The covergroups in the coverage directory are only available for instructions that operate on integer registers.

So far, there are two additional classes of registers in RISC-V:

• floating-point registers (with different FLEN for F, D, Zfh, Q)
• vector registers (with implementation-specific VLEN)

Are there plans to add support for them?

[pawks]

The covergroups for the F & D extensions do exist(link). However, no Vector support is available currently. Note that the coverage files in this repo are outdated and will soon be purged from the repository.