Warning messages about missing CSRs from new macro code in arch_test.h
ssecatch-w opened this issue · 3 comments
There's no explanation about how they should be set.
Ie, if I create them and set them to empty, what does this do to the test sequence? Is this acceptable functionality?
riscv-test-suite/env/arch_test.h: Assembler messages:
riscv-test-suite/env/arch_test.h:749: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
riscv-test-suite/env/arch_test.h:753: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
...
arch_test.h:
//==============================================================================
// Helper macro to set defaults for undefined interrupt set/clear
// macros. This is used to populated the interrupt vector table
//==============================================================================
//****************************************************************
#define RVTEST_DFLT_INT_HNDLR j cleanup_epilogs
//Mmode interrupts
#ifndef RVMODEL_SET_MSW_INT
.warning "RVMODEL_SET_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning"
#define RVMODEL_SET_MSW_INT RVTEST_DFLT_INT_HNDLR
#endif
...
This issue threw me and my students because riscof suddenly started producing lots of warnings.
To be very concrete, I've made the warnings go away by adding the following #defines before the #endif in the following two files:
riscof/sail_cSim/env/model_test.h
riscof/spike/env/model_test.h
#define RVMODEL_CLR_MSW_INT
#define RVMODEL_CLR_MTIMER_INT
#define RVMODEL_CLR_MEXT_INT
#define RVMODEL_SET_SSW_INT
#define RVMODEL_CLR_SSW_INT
#define RVMODEL_CLR_STIMER_INT
#define RVMODEL_CLR_SEXT_INT
#define RVMODEL_SET_VSW_INT
#define RVMODEL_CLR_VSW_INT
#define RVMODEL_CLR_VTIMER_INT
#define RVMODEL_CLR_VEXT_INT