Warning messages about missing CSRs from new macro code in arch_test.h

[ssecatch-w]

There's no explanation about how they should be set.
Ie, if I create them and set them to empty, what does this do to the test sequence? Is this acceptable functionality?

riscv-test-suite/env/arch_test.h: Assembler messages:
riscv-test-suite/env/arch_test.h:749: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
riscv-test-suite/env/arch_test.h:753: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
...

arch_test.h:
//==============================================================================
// Helper macro to set defaults for undefined interrupt set/clear
// macros. This is used to populated the interrupt vector table
//==============================================================================
//****************************************************************
#define RVTEST_DFLT_INT_HNDLR j cleanup_epilogs
//Mmode interrupts
#ifndef RVMODEL_SET_MSW_INT
.warning "RVMODEL_SET_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning"
#define RVMODEL_SET_MSW_INT RVTEST_DFLT_INT_HNDLR
#endif
...

[allenjbaum]

These macros are only used during interrupt tests, and are used to clear the interrupts so they don't keep interrupting after returning from the trap handler. If you aren't running interrupt tests, and don't define it: you get a warning, and the tests running with no issues If you aren't running interrupt tests, and do define it, the warning is suppressed, macro is never run, so it pretty much doesn't matter what the definition is . If you are running interrupt tests and don't define it - the test will en prematurely If you are running interrupt tests and define it as empty- then upon return from the trap handler it is likely to interrupt again, so no forward progress. If you are running interrupt tests and define it as a write to some model specific address that causes the interrupt wire to be deasserted, the test continues.

…

On Wed, Apr 26, 2023 at 10:16 AM ssecatchseagate ***@***.***> wrote: There's no explanation about how they should be set. Ie, if I create them and set them to empty, what does this do to the test sequence? Is this acceptable functionality? riscv-test-suite/env/arch_test.h: Assembler messages: riscv-test-suite/env/arch_test.h:749: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning riscv-test-suite/env/arch_test.h:753: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning ... arch_test.h: //============================================================================== // Helper macro to set defaults for undefined interrupt set/clear // macros. This is used to populated the interrupt vector table //============================================================================== //**************************************************************** #define RVTEST_DFLT_INT_HNDLR j cleanup_epilogs //Mmode interrupts #ifndef RVMODEL_SET_MSW_INT .warning "RVMODEL_SET_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning" #define RVMODEL_SET_MSW_INT RVTEST_DFLT_INT_HNDLR #endif ... — Reply to this email directly, view it on GitHub <#336>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJXTIKY7UKJ3GOCK2M3XDFJ5VANCNFSM6AAAAAAXMXQKQ4> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[davidharrishmc]

This issue threw me and my students because riscof suddenly started producing lots of warnings.

To be very concrete, I've made the warnings go away by adding the following #defines before the #endif in the following two files:

riscof/sail_cSim/env/model_test.h
riscof/spike/env/model_test.h

#define RVMODEL_CLR_MSW_INT
#define RVMODEL_CLR_MTIMER_INT
#define RVMODEL_CLR_MEXT_INT
#define RVMODEL_SET_SSW_INT
#define RVMODEL_CLR_SSW_INT
#define RVMODEL_CLR_STIMER_INT
#define RVMODEL_CLR_SEXT_INT
#define RVMODEL_SET_VSW_INT
#define RVMODEL_CLR_VSW_INT
#define RVMODEL_CLR_VTIMER_INT
#define RVMODEL_CLR_VEXT_INT

[allenjbaum]

That’s fine as long was you’re not actually running interrupt tests that might need to use them. Then- depending on the HW implementation - tests would fail because the model won’t know how to clear the interrupts. The other alternative is to just remove the warning messages.

…

On Sunday, May 14, 2023, David Harris ***@***.***> wrote: This issue threw me and my students because riscof suddenly started producing lots of warnings. To be very concrete, I've made the warnings go away by adding the following #defines before the #endif in the following two files: riscof/sail_cSim/env/model_test.h riscof/spike/env/model_test.h #define RVMODEL_CLR_MSW_INT #define RVMODEL_CLR_MTIMER_INT #define RVMODEL_CLR_MEXT_INT #define RVMODEL_SET_SSW_INT #define RVMODEL_CLR_SSW_INT #define RVMODEL_CLR_STIMER_INT #define RVMODEL_CLR_SEXT_INT #define RVMODEL_SET_VSW_INT #define RVMODEL_CLR_VSW_INT #define RVMODEL_CLR_VTIMER_INT #define RVMODEL_CLR_VEXT_INT — Reply to this email directly, view it on GitHub <#336 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJSNBERUHMKLLD7WYPTXGCYDZANCNFSM6AAAAAAXMXQKQ4> . You are receiving this because you commented.Message ID: ***@***.***>