All tests failing due to undefined macros??

Question

All tests failing due to undefined macros??

InspireSemi opened this issue a year ago · 3 comments

All of a sudden all our tests are failing due to these macros being undefined??

[1;31m ERROR [0m | [1;31mhttp://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h: Assembler messages:
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:760: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:764: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:768: Warning: RVMODEL_CLR_MEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:773: Warning: RVMODEL_SET_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:777: Warning: RVMODEL_CLR_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:781: Warning: RVMODEL_CLR_STIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:785: Warning: RVMODEL_CLR_SEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:790: Warning: RVMODEL_SET_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:794: Warning: RVMODEL_CLR_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:798: Warning: RVMODEL_CLR_VTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning
http://192.168.15.15:8080/job/riscvarchtest_c/ws/riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:802: Warning: RVMODEL_CLR_VEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning

We cannot make changes that break things like this. If a company has regression testing (Jenkins) going (like us) then all of a sudden tests blow up and what they thought was passing is now failing. Causing more work for someone to go figure out what has happened??

As I have said before the more roadblocks we put in place (intentional or not) the fewer people will be willing to invest the time and $$ to use this to "brand" their SOC.

Going forward any changes should be backwards compatible or if they will break things a major release should be made with announcements that you have to change things..

Answer 1 · 2023-05-22T19:43:10.000Z

Not sure now what is going on. I am running locally outside of Jenkins and it is working???
Very strange...

I will reopen if I find a smoking gun..

Answer 2 · 2023-05-22T21:46:01.000Z

It’s a warning, not an error. I’m not sure why it is indicating that a warning is an error- unless you are testing interrupts. You can define them all to be empty macros to remove the messages, just as the warning indicates.

…

On Monday, May 22, 2023, InspireSemi ***@***.***> wrote: All of a sudden all our tests are failing due to these macros being undefined?? [1;31m ERROR [0m | [1;31mhttp://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h: Assembler messages: http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:760: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:764: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:768: Warning: RVMODEL_CLR_MEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:773: Warning: RVMODEL_SET_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:777: Warning: RVMODEL_CLR_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:781: Warning: RVMODEL_CLR_STIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:785: Warning: RVMODEL_CLR_SEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:790: Warning: RVMODEL_SET_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:794: Warning: RVMODEL_CLR_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:798: Warning: RVMODEL_CLR_VTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:802: Warning: RVMODEL_CLR_VEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning We cannot make changes that break things like this. If a company has regression testing (Jenkins) going (like us) then all of a sudden tests blow up and what they thought was passing is now failing. Causing more work for someone to go figure out what has happened?? As I have said before the more roadblocks we put in place (intentional or not) the fewer people will be willing to invest the time and $$ to use this to "brand" their SOC. Going forward any changes should be backwards compatible or if they will break things a major release should be made with announcements that you have to change things.. — Reply to this email directly, view it on GitHub <#354>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJVGB5JU3ULSRZL3N2LXHOMF5ANCNFSM6AAAAAAYKXDO5Q> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

Answer 3 · 2023-05-23T13:16:48.000Z

Not sure what is going on… Somewhere between the 12th and the 19th everything broke… Marc Karasek Principal Software Engineer M: 678.770.3788 [A close up of a sign Description automatically generated] www.inspiresemi.com<http://www.cryptocoretech.com/> THIS MESSAGE IS INTENDED ONLY FOR THE USE OF THE INDIVIDUAL OR ENTITY TO WHICH IT IS ADDRESSED AND MAY CONTAIN INFORMATION THAT IS PRIVILEGED, CONFIDENTIAL AND/OR EXEMPT FROM DISCLOSURE UNDER APPLICABLE LAW. If the reader of this message is not the intended recipient or agent responsible for delivering the message to the intended recipient, then you are hereby notified that any dissemination or copying of this communication is strictly prohibited. If you have received this electronic transmission in error, please delete it from your system without copying it and notify the sender by reply e-mail so that our address record can be corrected. Thank you. From: Allen Baum ***@***.***> Sent: Monday, May 22, 2023 5:46 PM To: riscv-non-isa/riscv-arch-test ***@***.***> Cc: Marc Karasek ***@***.***>; State change ***@***.***> Subject: Re: [riscv-non-isa/riscv-arch-test] All tests failing due to undefined macros?? (Issue #354) It’s a warning, not an error. I’m not sure why it is indicating that a warning is an error- unless you are testing interrupts. You can define them all to be empty macros to remove the messages, just as the warning indicates.

On Monday, May 22, 2023, InspireSemi ***@***.***<mailto:***@***.***>> wrote: All of a sudden all our tests are failing due to these macros being undefined?? [1;31m ERROR [0m | [1;31mhttp://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h: Assembler messages: http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:760: Warning: RVMODEL_CLR_MSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:764: Warning: RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:768: Warning: RVMODEL_CLR_MEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:773: Warning: RVMODEL_SET_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:777: Warning: RVMODEL_CLR_SSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:781: Warning: RVMODEL_CLR_STIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:785: Warning: RVMODEL_CLR_SEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:790: Warning: RVMODEL_SET_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:794: Warning: RVMODEL_CLR_VSW_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:798: Warning: RVMODEL_CLR_VTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning http://192.168.15.15:8080/job/riscvarchtest_c/ws/ riscvarchtest/riscv-arch-test/riscv-test-suite/env/arch_test.h:802: Warning: RVMODEL_CLR_VEXT_INT not defined. Executing this will end test. Define an empty macro to suppress this warning We cannot make changes that break things like this. If a company has regression testing (Jenkins) going (like us) then all of a sudden tests blow up and what they thought was passing is now failing. Causing more work for someone to go figure out what has happened?? As I have said before the more roadblocks we put in place (intentional or not) the fewer people will be willing to invest the time and $$ to use this to "brand" their SOC. Going forward any changes should be backwards compatible or if they will break things a major release should be made with announcements that you have to change things.. — Reply to this email directly, view it on GitHub <https://url.avanan.click/v2/___https://github.com/riscv-non-isa/riscv-arch-test/issues/354<https://url.avanan.click/v2/___https:/github.com/riscv-non-isa/riscv-arch-test/issues/354>>___.YXAzOmluc3BpcmVzZW1pOmE6bzozNDU1OTE4NzlmMmM4NTdlMDdlMWI2ZTU4ODcxNjZmMDo2OjUyMjI6MzY4YTk3ODU1OTM2NTRmODE1ZWJiOGNiNTI4YWU4NzE1NTlhYTQ4ZmFlYzZmNmFjOGRkNzQ2ZTZlZmMyNGU4NTp0OlQ;, or unsubscribe <https://url.avanan.click/v2/___https://github.com/notifications/unsubscribe-auth/AHPXVJVGB5JU3ULSRZL3N2LXHOMF5ANCNFSM6AAAAAAYKXDO5Q<https://url.avanan.click/v2/___https:/github.com/notifications/unsubscribe-auth/AHPXVJVGB5JU3ULSRZL3N2LXHOMF5ANCNFSM6AAAAAAYKXDO5Q>>___.YXAzOmluc3BpcmVzZW1pOmE6bzozNDU1OTE4NzlmMmM4NTdlMDdlMWI2ZTU4ODcxNjZmMDo2OjEyYTc6MjA2YWUwNzcyYzcyY2QyMTU4NzNiMWQxNzQyYzhmOGY1MDYzMTMzMmJjZDYzZmIzN2JhNWZmNTMwNjk0MzM1Yzp0OlQ; . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***<mailto:***@***.***>>

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