Atomic Test cases for amominu (and potentially others) Sail is not generating the correect signature

[InspireSemi]

Ref.disass code for inst_0 for amominu.w
0000000080000400 <inst_0>:
80000400: bff00f13 li t5,-1025
80000404: 01e0b023 sd t5,0(ra)
80000408: fff00f13 li t5,-1
8000040c: 03ff1f13 slli t5,t5,0x3f
80000410: 00008f93 mv t6,ra
80000414: c1efafaf amominu.w t6,t5,(t6)
80000418: 01f0b423 sd t6,8(ra)

The first signature should have been FFFF FFFF FFFF FBFF What Sail is storing is: FFFF_FFFF_0000_0000
I have not looked further into the signature to see if others are also wrong.

I have attached all the files from the ref dir under riscof_work for amominu.w

amominu.w.zip

[allenjbaum]

If I am understanding this correctly , memory has the value FFFF FFFF FFFF FFBF register has the value 8000 0000 0000 0000 amominu will replace the value in memory with the unsigned minimum of the lower 32bits of each, and put the sign extended low 32bits into rd. So, the unsigned min of (FFFF FFBF, 0000 0000), is 0000 0000, What you should be seeing in the signature is the upper half unchanged and upper half updated with the min (FFFF FFFF 0000 0000). What you should be seeing in the signature+8 is the original value in memory, (FFFF FFFF FFFF FFBF) So Sail is doing the right thing, as far as I can tell. (And, if this were an actual bug, it should be filed against riscv-sail, not against riscv-arch-test

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On Tue, Jan 23, 2024 at 8:05 AM InspireSemi ***@***.***> wrote: Ref.disass code for inst_0 for amominu.w 0000000080000400 <inst_0>: 80000400: bff00f13 li t5,-1025 80000404: 01e0b023 sd t5,0(ra) 80000408: fff00f13 li t5,-1 8000040c: 03ff1f13 slli t5,t5,0x3f 80000410: 00008f93 mv t6,ra 80000414: c1efafaf amominu.w t6,t5,(t6) 80000418: 01f0b423 sd t6,8(ra) The first signature should have been FFFF FFFF FFFF FBFF What Sail is storing is: FFFF_FFFF_0000_0000 I have not looked further into the signature to see if others are also wrong. I have attached all the files from the ref dir under riscof_work for amominu.w amominu.w.zip <https://github.com/riscv-non-isa/riscv-arch-test/files/14026954/amominu.w.zip> — Reply to this email directly, view it on GitHub <#430>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJST3JKOYNU5QTU3ZF3YP7NV5AVCNFSM6AAAAABCHICRJ2VHI2DSMVQWIX3LMV43ASLTON2WKOZSGA4TMNBSG44TGOA> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>