ecall check fails in CLIC mode

[silabs-kjetil]

This issue is only seen when using CLIC mode trap handling

https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L1160

This code is supposed to check for ecall, and exit early when it is detected. However the way the code is doing this does not work correctly when mcause contains extra bits like in the case when CLIC is used. Typically bits 29:28 will contain 0b11 so mcause will somtimes have the value 0x3000000B when read by the handler and the code will not detect that this is actually an ecall with exception code = 0xB.

This issue has also been discussed in the following PR: #436 (comment)

[allenjbaum]

Ah; are there any other bits that might be set for an exception?

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On Mon, Mar 11, 2024 at 1:24 AM Kjetil Østerås ***@***.***> wrote: This issue is only seen when using CLIC mode trap handling https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L1160 This code is supposed to check for ecall, and exit early when it is detected. However the way the code is doing this does not work correctly when mcause contains extra bits like in the case when CLIC is used. Typically bits 29:28 will contain 0b11 so mcause will somtimes have the value 0x3000000B when read by the handler and the code will not detect that this is actually an ecall with exception code = 0xB. This issue has also been discussed in the following PR: #436 (comment) <#436 (comment)> — Reply to this email directly, view it on GitHub <#440>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJXHFRCTS6PYVUW27PDYXVS3VAVCNFSM6AAAAABEP2U7X2VHI2DSMVQWIX3LMV43ASLTON2WKOZSGE3TQNJRG4ZTCMI> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[allenjbaum]

It looks like this check should clear bits XLEN-2..12 before checking . We may have to make a larger change and store all of mcause instead of just the upper and lower bits then. On Tue, Mar 19, 2024 at 9:17 PM Allen Baum ***@***.***> wrote:

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Ah; are there any other bits that might be set for an exception? On Mon, Mar 11, 2024 at 1:24 AM Kjetil Østerås ***@***.***> wrote: > This issue is only seen when using CLIC mode trap handling > > > https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L1160 > > This code is supposed to check for ecall, and exit early when it is > detected. However the way the code is doing this does not work correctly > when mcause contains extra bits like in the case when CLIC is used. > Typically bits 29:28 will contain 0b11 so mcause will somtimes have the > value 0x3000000B when read by the handler and the code will not detect that > this is actually an ecall with exception code = 0xB. > > This issue has also been discussed in the following PR: #436 (comment) > <#436 (comment)> > > — > Reply to this email directly, view it on GitHub > <#440>, or > unsubscribe > <https://github.com/notifications/unsubscribe-auth/AHPXVJXHFRCTS6PYVUW27PDYXVS3VAVCNFSM6AAAAABEP2U7X2VHI2DSMVQWIX3LMV43ASLTON2WKOZSGE3TQNJRG4ZTCMI> > . > You are receiving this because you are subscribed to this thread.Message > ID: ***@***.***> >

[allenjbaum]

Actually, no - we already save all of mcause On Tue, Mar 19, 2024 at 9:29 PM Allen Baum ***@***.***> wrote:

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It looks like this check should clear bits XLEN-2..12 before checking . We may have to make a larger change and store all of mcause instead of just the upper and lower bits then. On Tue, Mar 19, 2024 at 9:17 PM Allen Baum ***@***.***> wrote: > Ah; are there any other bits that might be set for an exception? > > On Mon, Mar 11, 2024 at 1:24 AM Kjetil Østerås ***@***.***> > wrote: > >> This issue is only seen when using CLIC mode trap handling >> >> >> https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L1160 >> >> This code is supposed to check for ecall, and exit early when it is >> detected. However the way the code is doing this does not work correctly >> when mcause contains extra bits like in the case when CLIC is used. >> Typically bits 29:28 will contain 0b11 so mcause will somtimes have the >> value 0x3000000B when read by the handler and the code will not detect that >> this is actually an ecall with exception code = 0xB. >> >> This issue has also been discussed in the following PR: #436 (comment) >> <#436 (comment)> >> >> — >> Reply to this email directly, view it on GitHub >> <#440>, or >> unsubscribe >> <https://github.com/notifications/unsubscribe-auth/AHPXVJXHFRCTS6PYVUW27PDYXVS3VAVCNFSM6AAAAABEP2U7X2VHI2DSMVQWIX3LMV43ASLTON2WKOZSGE3TQNJRG4ZTCMI> >> . >> You are receiving this because you are subscribed to this thread.Message >> ID: ***@***.***> >> >

[silabs-kjetil]

Yes there might be other bits that are set, so in the case when CLIC is used we have to only look at bits 11:0 to inspect the exception/interrupt code. Here is a picture of the changes done to xcause for CLIC mode.

It looks like the arch_test.h file already contains a mask to extract the exception cause bits, however this is not used when checking for an ecall.

exception mask: https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L157

[allenjbaum]

Ecall is known and is required, so we don't need that mask in this case. We only do the ecall check when we know it's an interrupt (sign=0). In any case, the fix is in, and I just need to get someone to test it. We will check if sign=0 and bits 11:0= 0x8..0xB

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On Wed, Mar 20, 2024 at 12:25 AM Kjetil Østerås ***@***.***> wrote: Yes there might be other bits that are set, so in the case when CLIC is used we have to only look at bits 11:0 to inspect the exception/interrupt code. Here is a picture of the changes done to xcause for CLIC mode. bilde.png (view on web) <https://github.com/riscv-non-isa/riscv-arch-test/assets/102311786/abcbcbd4-1a72-4792-ac2b-12152d3c82ff> It looks like the arch_test.h file already contains a mask to extract the exception cause bits, however this is not used when checking for an ecall. exception mask: https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/env/arch_test.h#L157 — Reply to this email directly, view it on GitHub <#440 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJRMO33GDENT6XDR4C3YZE2YFAVCNFSM6AAAAABEP2U7X2VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMBYHE2DAMZYGA> . You are receiving this because you commented.Message ID: ***@***.***>