riscv-non-isa/riscv-external-debug-security
The RISC-V External Debug Security Specification
MakefileCC-BY-4.0
Issues
- 4
Elaborate on trace related sideband signal
#48 opened by AoteJin - 1
Quick Access behavior when debug is disallowed
#50 opened by AoteJin - 3
- 13
Per priviledge-mode debug control
#12 opened by joxie - 5
Trigger registers accessibility in debug mode
#49 opened by AoteJin - 8
External Trigger of Core Trigger Module
#9 opened by joxie - 10
spec v0.5 ch 1 - ch 3 feedback
#36 opened by bcstrongx - 3
spec v0.5 ch 4 - end feedback
#37 opened by bcstrongx - 2
aamvirtual restriction is not required
#35 opened by gokhankaplayan - 2
sec_check in VS/U-mode is not defined?
#34 opened by zhangdujiao - 5
Behaviour on an illegal write value attempt (M-mode) to DCSR.PRV (debug access privilege)
#31 opened by sudheendraks - 5
ecall/xret behaviour in debug mode
#27 opened by gokhankaplayan - 2
Naming of Zedsec
#29 opened by pdonahue-ventana - 3
Add control nob to ndmreset
#20 opened by joxie - 3
Discovery of ext. debug sec. spec
#21 opened by joxie - 3
Security fault reported as cmderr
#16 opened by vicky-goode-img - 3
mdbgen as global input instead of per-hart
#23 opened by gokhankaplayan - 1
- 4
- 1
- 11
Interaction with trace
#11 opened by joxie - 4
Performance Counter enable for M-mode
#8 opened by joxie - 1
- 1
Mandate the behavior of asynchronous trigger
#14 opened by joxie - 0
External Trigger of Core Trigger Module
#13 opened by joxie