riscv-non-isa/riscv-iommu

Question about address of msipte when the offset may be out of 4K range

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viktoryou commented

From the Chapter 2.3.3 of spec, in the process to translate addresses of MSIs,

  1. Extract an interrupt file number I from A as I = extract(A >> 12, DC.msi_addr_mask) ...
  2. Let m be (DC.msiptp.PPN x 2^12).
  3. Let msipte be the value of sixteen bytes at address (m | (I x 16))...

The model uses m + ( I * 16 ) as the address of msipte. However they are not equivalent when I * 16 is out of 4K range. I could not see any guarantee of that, neither from the extract function nor restriction of msi_addr_mask configuration. Is it expected that I * 16 may be out of 4K range? What should be the outcome when it is allowed and triggered?

ved-rivos commented

An MSI page table is a flat array of MSI page table entries , each 16 bytes. MSI page tables have no multi-level hierarchy like regular RISC-V page tables do. The definition of the table is provided by the AIA specification:

The number of entries in an MSI page table is 2^k where k is the number of bits that are ones in the MSI address mask used to extract the interrupt file number from the destination guest physical address. If an MSI page table has 256 or fewer entries, the start of the table is aligned to a 4-KiB page address in real physical memory. If an MSI page table has 2^k > 256 entries, the table must be naturally aligned to a 2^k × 16-byte address boundary. If an MSI page table is not aligned as required, all entries in the table appear to an IOMMU as unspecified, and any address an IOMMU may compute and use for reading an individual MSI PTE from the table is also unspecified.

Is it expected that I * 16 may be out of 4K range? What should be the outcome when it is allowed and triggered?

Yes, its legal for I * 16 to be beyond 4K.