riscv-non-isa/riscv-iommu

why not set `g_reg_file.ipsr.cip = 1;` after generate_interrupt?

baimengwei opened this issue · 1 comments

baimengwei commented

If the conditions to set that bit are still present (See <<IPSR_FIELDS>>) or if they occur after the bit is cleared then that
bit transitions again from 0->1.

https://github.com/riscv-non-isa/riscv-iommu/blob/main/iommu_ref_model/libiommu/src/iommu_reg.c#L505C1-L515C14

            if ( ipsr_temp.cip == 1 )
                g_reg_file.ipsr.cip = 0;
            if ( ipsr_temp.cip == 1 ) {
                if ( (g_reg_file.cqcsr.cmd_to ||
                      g_reg_file.cqcsr.cmd_ill ||
                      g_reg_file.cqcsr.cqmf ||
                      g_reg_file.cqcsr.fence_w_ip) && 
                     (g_reg_file.cqcsr.cie == 1) ) {
                    generate_interrupt(COMMAND_QUEUE);
                }
            }

it seems that generate_interrupt(COMMAND_QUEUE); lack a g_reg_file.ipsr.cip = 1 ?

ved-rivos commented

it seems that generate_interrupt(COMMAND_QUEUE); lack a g_reg_file.ipsr.cip = 1 ?

See here.

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