riscv-non-isa/riscv-trace-spec

sec_check optional sideband signal mentioned in RISC-V External Debug Security Extension

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Chatpter 3.2. Trace mentioned: "The extension requires that trace availability from each hart is constrained by default. When Zedsec is supported, the optional sideband signal to trace encoder, sec_check[i] [2], must be implemented for each hart i, and this signal must be reset to 1. "

But I didn't see the optional sideband signal: sec_check[i] signal from https://github.com/riscv-non-isa/riscv-trace-spec in Chapter 4.2.3..

Thanks a lot!
That is to say, sec_check sideband signal will be added to the ingress port eventually, and it may takes months to finish.

This will require at best a fast-track process and realistically will take many months to complete.