riscv-non-isa/riscv-trace-spec

tvalepc for illegal instruction

weiqi7777 opened this issue · 2 comments

hi:
from table 7.2, the tvalepc description:

Exception address if ecause is 2 and interrupt is 0(illegal instruction exception), or trap value otherwise

but for section 7.3.1.

This field reports the address of illegal instructions, or the trap value otherwise. This ensures
that the address of the faulting instruction is reported for all required cases. The trap value is
set to the address of the faulting instruction for hardware breakpoints, access or page faults and
instructions, loads or stores that are mis-aligned, but not for illegal instructions (for which it is set
to the opcode)

the two descriptions are not match for illegal instruction.
which description is correct?

thanks
lujun

thanks for yout replay