riscv-non-isa/riscv-trace-spec

Report timing of context

hwliu-tommy opened this issue · 4 comments

hwliu-tommy commented

Hi,

I have 2 questions about the report timing of context.

If the context value (comes from CSR) is updated by a CSRRW instruction, which instruction should report the new context?

  1. On the CSRRW instruction, report the next value of context (value from CSR write data)
  2. On the next instruction, report the current value of context

And the other question is that can the context be reported with a block that only contains exception or interrupt?

Thanks,
Tommy

IainCRobertson commented
hwliu-tommy commented

Hi, Iain,

Thanks for your reply.
It is very clear for question 1.

Sorry I didn't describe question 2 clearly.
The question is asking about the core to encoder interface.
Can the core reports context to encoder when itype=interrupt/exception, and iretire=0?

Since the spec says

Context for all instructions retired on this cycle. (context definition)
Report the address of the 1st instruction retired in this block, and the new context. (from ctype = report precisely)

My interpretation is that the context change can only be reported when the next instruction is retired.
If the next instruction raises an exception and not being retired, the context won't be reported.

So there will be a corner case when an exception happens right after a context change.
For the following sequence:

1. CSRRW set context to 0 (itype=0, iretire=2)
2. exception taken, set context to 1 (itype=1, iretire=0)
3. instruction retired with context = 1 (itype=0, iretire=2)

If the context can only be reported on instruction retire, the context information before the exception taken might not be observed through trace.

Thanks,
Tommy

IainCRobertson commented
hwliu-tommy commented

Hi, Iain,

Thank for the reply.
The clarification is very clear and it resolves my question.
And sorry for my late reply.

Thanks,
Tommy