riscv/riscv-opcodes

Does rvv-opcodes include all instructions in rvv-1.0?

naveen126 opened this issue · 1 comments

naveen126 commented

Hi Sir,
I have some problems.
(1) I can not find some instructions in rvv-opcodes, such as vlseg3e32 and vluxseq3ei32.v, ...
(2) vslideup.vi has a unsigned imm5, but it has simm5 in rvv-opcodes.

Please give confirmation for these problems.

Thanks!

aswaterman commented

(1) The nf field distinguishes segment loads/stores from regular loads/stores. For example, vlseg3e32.v is the nf=2 case of this instruction:

riscv-opcodes/opcodes-rvv

Line 25 in 2497a8c

vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07

(2) rvv-opcodes is only concerned with the bit positions of the operands, not their meanings. So there is no distinction between simm5 and uimm5.