riscv/riscv-opcodes

Update CLIC CSR_xINTSTATUS addresses, add CSR_xINTTHRESH

Opened this issue · 1 comments

dansmathers commented

update CSR_MINTSTATUS, CSR_SINTSTATUS, CSR_UINTSTATUS addresses to read-only csr addresses and add CSR_MINTTHRESH, CSR_SINTTHRESH, CSR_UINTTHRESH csrs.

spec: https://github.com/riscv/riscv-fast-interrupt

Please see pull #226

dansmathers commented

pinging. Can this be reviewed? It holds up sail/arch tests/spike/gcc/llvm. Thanks