riscv/riscv-opcodes

The instructions vsll.vi, vsrl.vi and vsra.vi use zero-extended 5-bit immediate

Opened this issue 3 years ago · 1 comments

XuJiandong commented 3 years ago

According to: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#116-vector-single-width-shift-instructions

But in https://github.com/riscv/riscv-opcodes/blob/master/opcodes-rvv
"simm5" is used. I think it should be "zimm5" instead.

aswaterman commented 3 years ago

It doesn't really matter; simm5 has no semantic meaning. It's just a token that means "bits 19..15".