rmflyer

rmflyer's Stars

• emrii/verilog-file-parser

  This automated script will parse through a verilog file RTL code and identify the module, its ports and parametrs. The path to the file should be given as an arguement on the command line, the result will be stored in a new file named 'LOG<name_of_module>.text'

  Language:Python1

• tree-sitter/tree-sitter-verilog

  SystemVerilog grammar for tree-sitter

  Language:JavaScript9336

• kevinpt/hdlparse

  Simple parser for extracting VHDL documentation

  Language:Python7054

• Nic30/hdlConvertorAst

  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

  Language:Python317

• Miracle3310/VerilogParser

  A Verilog HDL parser based on Python, can be used to generate testbench.

  Language:Python4

• olofk/edalize

  An abstraction library for interfacing EDA tools

  Language:Python641191

• controlpaths/verilog_parser

  A python based verilog parser

  Language:Python191

• cclienti/svmodule

  SystemVerilog & Verilog Module I/O parser and printer

  Language:Python254

• jimwang99/parser-for-chip-design

  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

  Language:Python277