robertstar

Research in DSP, digital communications and FPGA design.

Russia, Saint-Petersburg

Pinned Repositories

AGC
Language:SystemVerilog00
BFSK_DEMOD
Language:SystemVerilog00
BFSK_MOD
Language:SystemVerilog00
BUKS2
Language:SystemVerilog00
BUKS2_imitator32ch
Language:SystemVerilog00
CANDA-SPI-ADC
00
CANDA-SPI-SO
Language:VHDL00
CANDA-SPI-SO-FD
Language:VHDL00
Ethernet_ddr3_fifo_dac
Language:VHDL12
SPLL
Simple PLL
Language:Verilog2 1 00

robertstar's Repositories

robertstar/SPLL
Simple PLL
Language:Verilog2 1 00
robertstar/Ethernet_ddr3_fifo_dac
Language:VHDL12
robertstar/AGC
Language:SystemVerilog00
robertstar/BFSK_DEMOD
Language:SystemVerilog00
robertstar/BFSK_MOD
Language:SystemVerilog00
robertstar/BUKS2
Language:SystemVerilog00
robertstar/BUKS2_imitator32ch
Language:SystemVerilog00
robertstar/CANDA-SPI-ADC
00
robertstar/CANDA-SPI-SO
Language:VHDL00
robertstar/CANDA-SPI-SO-FD
Language:VHDL00
robertstar/FACTOR1_BINS
Language:VHDL1 0
robertstar/FACTOR1_SKP_DSP
Language:VHDL
robertstar/FACTOR2_SKP
Language:VHDL
robertstar/JFactorViewer
Language:Java
robertstar/JLogViewer
robertstar/JSpiSoViewer
robertstar/QFactorViewer
Language:C++
robertstar/QPCAP_test
Language:C++1 0