FPGA-SDR
DE2-115 based controller for NI USRP 2920
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Create an empty Quartus II project called final_ethernet_controller.
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Add all files in repository HDL folder to the project directory and add them in Quartus.
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Move nios_system.qsys from the repository Qsys folder into the project directory.
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Open Qsys in Quartus and open nios_system.qsys.
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Generate the HDL in Qsys.
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Add the nios_system.qip created to the project.
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Replace final_ethernet_controller.qsf in the project directory with final_ethernet_controller.qsf from the repository. Add the .sdc file from the timing repository folder and add to project.
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Open Eclipse from Quartus and create new Nios II project with BSP.
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Use the nios_system.sopc created when the Nios was built. Make sure the project is blank.
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Drag all code from the Nios C Code repository folder into the eclipse project.
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Build the BSP and then the project and run as Nios II hardware