Pinned Repositories
eeenote-kernel
EeeNote EA-800 support for mainline kernel
lomiloop
Wideband 50 kHz to 30 MHz small receiving loop antenna amplifier
loran_datatest
Loran-C signal locking and tracking software. Test version that reads signal from file
LoranC
LORAN C (USSR "Chayka") receiver project
lwdo-sdr-fw
LWDO-SDR firmware (FPGA & FTDI)
lwdo-sdr-hw
LWDO-SDR - experimental LF/VLF SDR timing receiver
metra-m1t380-doc
Metra M1T380 multimeter documentation and reverse-engineering
pymenuconfig
Frontend to Kconfiglib based on Tkinter that resembles classic 'menuconfig'
rs_matlab
Reed-Solomon over GF(2^m) implementation in MATLAB 2011a
winnwt5
Control application for NWT network analyzers
romavis's Repositories
romavis/pymenuconfig
Frontend to Kconfiglib based on Tkinter that resembles classic 'menuconfig'
romavis/winnwt5
Control application for NWT network analyzers
romavis/rs_matlab
Reed-Solomon over GF(2^m) implementation in MATLAB 2011a
romavis/lwdo-sdr-fw
LWDO-SDR firmware (FPGA & FTDI)
romavis/lomiloop
Wideband 50 kHz to 30 MHz small receiving loop antenna amplifier
romavis/LoranC
LORAN C (USSR "Chayka") receiver project
romavis/lwdo-sdr-hw
LWDO-SDR - experimental LF/VLF SDR timing receiver
romavis/eeenote-kernel
EeeNote EA-800 support for mainline kernel
romavis/loran_datatest
Loran-C signal locking and tracking software. Test version that reads signal from file
romavis/metra-m1t380-doc
Metra M1T380 multimeter documentation and reverse-engineering
romavis/metra-m1t380-tools
Tools for hacking Metra M1T380 multimeter
romavis/STM32_Experiments
Custom embedded printf(), float-to-string conversion, STM32F4 init routintes..
romavis/connect-minifit.pretty
KiCad Pcbnew modules: Molex Mini-Fit-like connectors
romavis/hpglope
Emualtes HPGL plotter on a UART port, plots received pages and saves to PNG or PDF
romavis/pyftdi
FTDI device driver written in pure Python
romavis/pyOCD
Open source Python library for programming and debugging Arm Cortex-M microcontrollers
romavis/rggen-verilog-rtl
Common Verilog RTL modules for RgGen
romavis/romavis.github.io
romavis/verilog-axis
Verilog AXI stream components for FPGA implementation