rongcuid/riscv-megaproject
A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
VerilogBSD-3-Clause
Stargazers
- aa1397
- Alex-lhfeng
- annaswing
- AnttiLukats@micro-FPGA
- anyutianluo
- azuse未来ガジェット研究所
- ChrisHua96
- cisen
- goodplayerPP
- guxue365
- haozi23333kangne moe
- hxs120021
- kikajack深圳
- kuzicode
- lc-mayChina
- Lstaras
- Luke-li-Chen
- LuoXishuang0712
- mitoksimCalifornia
- MottIns
- RESBI
- slcmcu
- spacefanMgcSat
- strongwongxpev
- WhiteH-coder
- wlnirvana
- xiaoliyang1
- xinlnixChina
- xychen9459UESTC
- zilijing