roydhinakar's Stars
AngeloJacobo/FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
AngeloJacobo/FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
AngeloJacobo/FPGA_OV7670_Camera_Interface
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
AngeloJacobo/ULX3S_FPGA_Camera_Streaming
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
AngeloJacobo/FPGA_Book_Experiments
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
Reenforcements/VerilogDE2115AudioFilters
Student project for using audio on the DE2-115 FPGA development board.
MaxMorning/Handwritting-number-distinguishing-with-DNN-by-Nexys-4-DDR-in-Verilog-HDL
Digital Logic Lecture Final Project in the first term of year 2020-21
rahul0805/MIPS_processor
32 bit 2 stage pipelined MIPS processor.
rahul0805/DDR2_controller
DDR2 RAM controller in verilog
someone755/ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
adibis/DDR2_Controller
DDR2 memory controller written in Verilog
ultraembedded/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
yasnakateb/PipelinedARM
💎 A 32-bit ARM Processor Implementation in Verilog HDL
chsasank/ARM7
Implemetation of pipelined ARM7TDMI processor in Verilog
Omarchaban/AES
Implementation of AES-128 encryption algorithm on ZYNQ-7000 kit and using AXI protocol to interface with the IP. The RTL code was written in Verilog. This was the final project of Najah now Digital Design Diploma.
ckyrkou/Hardware_Design_Cores
IP Cores in Verilog and VHDL for arithmetic functions
risclite/ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
AleksandarKostovic/Riscy-SoC
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
ferozer/AMBA-AHB2APB-Bridge-protocol
The Advanced Microcontroller Bus Architecture (AMBA) is an on-chip bus architecture used to Design high performance embedded microcontrollers and strengthen the reusability of IP core and widely used interconnection standard for system on chip (SOC). AMBA AHB (advanced high performance bus) is the highperformance bus means higher bandwidth or high clock frequency system modules. AMBA APB (advanced peripheral bus) as the name suggest used to connect peripheral to the architecture, peripherals like UART, Timer, keypad, PIO etc. this are part of low performance bus and it is optimized for low power consumption and interface reduced complexity to support peripheral functions. In this the functions of the AHB2APB Bridge to make the signals compatible with the high performance bus i.e. AHB with low performance bus i.e. APB, to do so we have to write the DUT code in Verilog and all other test case code in system Verilog, further have verified all the functions of bridge protocol using QuestaSim tool. The code coverage and functional coverage and functional verification of the Bridge RTL design is 97% covered by using QuestaSim
Sanjeeet/Processor
Designed and Implemented a Processor in Verilog using DE1-SoC Board
biren15/Design-and-Implementation-of-a-Cruise-Control-System
- Designed RTL of cruise control system in Verilog and verified the design using Verilog testbench. - Synthesized the design using Design Vision and performed pre-layout Static Timing Analysis on the design using Synopsys Primetime. - Performed automatic place and route on the generated netlist using SoC Encounter.
WindowsAddict/IDM-Activation-Script
An open source tool to activate and reset trial of Internet Download Manager
subhra74/xdm
Powerfull download accelerator and video downloader
ketak-singh/Speech-Recognition-Simulation-using-Verilog
Our project aimed at developing a Real-Time Speech Recognition Engine on an FPGA using Altera DE2 board. The system was designed so as to recognize the word being spoken into the microphone. As large number of accents spoken around the world that this conundrum still remains an active area of research. Speech Recognition finds numerous applications including health care, artificial intelligence, human-computer interaction, Interactive Voice Response Systems, military, avionics, etc. Another most important application resides in helping physically-challenged people to interact with the world in a better way.
EECS150/project_skeleton_fa21
FPGA Project for EECS 151/251A (Fall 2021)
erosen/FPGA_Object_Tracking
ECE563 Final Project - FPGA based camera tracking
lllbbbyyy/FPGA-OV2640
This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
coderonion/awesome-cuda-and-hpc
🔥🔥🔥 A collection of some awesome public CUDA, cuBLAS, TensorRT and High Performance Computing (HPC) projects.
powerplayer9/Voice-Based-Motor-Control
A verilog HDL based project to control a servomotor with voice commands from an android phone.
Ahmadreza-SY/arm-verilog
Implementation of the ARM processor using verilog. (Univ. course project)