rpjayaraman

HW Engineer

VerifworksIndia

Pinned Repositories

RISCV_CPU_DESIGN-rpjayaraman
riscv_myth_workshop_nov22-rpjayaraman created by GitHub Classroom
11
af_pyslint
SystemVerilog Linter based on pyslang
Language:SystemVerilog00
CTB_2022-Hackathon
challenges-rpjayaraman created by GitHub Classroom
Language:Verilog00
python
`
Language:Python00
rpjayaraman
Config files for my GitHub profile.
01
svunit_verilator
Reference form Srini: https://github.com/svenka3/svunit/tree/srini_verilator
Language:SystemVerilog00
vlt-uvm
Verilator with UVM
Language:SystemVerilog00
vw_SVunit_verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++00
challenges-rpjayaraman
challenges-rpjayaraman created by GitHub Classroom
Language:Verilog11
RISCV_CPU_DESIGN-rpjayaraman
riscv_myth_workshop_nov22-rpjayaraman created by GitHub Classroom
02

rpjayaraman's Repositories

rpjayaraman/af_pyslint
SystemVerilog Linter based on pyslang
Language:SystemVerilog
rpjayaraman/vlt-uvm
Verilator with UVM
Language:SystemVerilog
rpjayaraman/svunit_verilator
Reference form Srini: https://github.com/svenka3/svunit/tree/srini_verilator
rpjayaraman/vw_SVunit_verilator
Verilator open-source SystemVerilog simulator and lint system
rpjayaraman/python
`
Language:Python
rpjayaraman/RISCV_CPU_DESIGN-rpjayaraman
riscv_myth_workshop_nov22-rpjayaraman created by GitHub Classroom
11
rpjayaraman/CTB_2022-Hackathon
challenges-rpjayaraman created by GitHub Classroom
rpjayaraman/rpjayaraman
Config files for my GitHub profile.
1