rsnikhil
Hardware design: mostly RISC-V, mostly using Bluespec BSV. Also Haskell, RISC-V Formal Specifications, tutorials.
Bluespec, Inc.Framingham, MA, USA
Pinned Repositories
Bluespec_BSV_Formal_Semantics
Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
DEVEL_Learn_Bluespec_and_RISCV_Design
Development area for another repo: Learn_Bluespec_and_RISCV_Design
Forvis_RISCV-ISA-Spec
Formal specification of RISC-V Instruction Set
goParseBSV
A standalone parser for BSV (Bluespec SystemVerilog) written in Go
ICFP2020_Bluespec_Tutorial
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
Learn_Bluespec_and_RISCV_Design
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
RISCV_ISA_Formal_Spec_in_BSV
A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
RISCV_ISA_Spec_Tour
Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
RISCV_Piccolo_v1
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
rsnikhil's Repositories
rsnikhil/Forvis_RISCV-ISA-Spec
Formal specification of RISC-V Instruction Set
rsnikhil/Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
rsnikhil/ICFP2020_Bluespec_Tutorial
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
rsnikhil/Learn_Bluespec_and_RISCV_Design
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
rsnikhil/RISCV_ISA_Spec_Tour
Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
rsnikhil/RISCV_Piccolo_v1
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
rsnikhil/RISCV_ISA_Formal_Spec_in_BSV
A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
rsnikhil/Bluespec_BSV_Formal_Semantics
Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
rsnikhil/goParseBSV
A standalone parser for BSV (Bluespec SystemVerilog) written in Go
rsnikhil/DEVEL_Learn_Bluespec_and_RISCV_Design
Development area for another repo: Learn_Bluespec_and_RISCV_Design
rsnikhil/RISC-V_Intro
rsnikhil/Enigma_Cryptol_Bluespec_BSV
Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
rsnikhil/Tutorial_at_HPCA-29
An AWS-FPGA Testbed for Architecture Research on RISC-V CPUs, Accelerators, and Memory Systems
rsnikhil/bsc
Bluespec Compiler (BSC)
rsnikhil/Multithreaded_Architectures_1993
Slides from Multithreaded Architectures tutorial 1993 by Rishiyur S. Nikhil
rsnikhil/Experimental_RISCV_Feature_Model
An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features
rsnikhil/sail-riscv
Sail RISC-V model
rsnikhil/bsc-contrib
A place to share libraries and utilities that don't belong in the core bsc repo
rsnikhil/Misc_Utilities
Miscellaneous Utilities
rsnikhil/EDB
Economical/Elementary Debugger
rsnikhil/Temporary_TGISA
Temporary work site for another project (please ignore until public announcement)