s72sharm

5-Stage-Pipelined-MIPS-Processor

http://sugandhasharma.weebly.com/computer-architecture--digital-vlsi.html

5-stage-Pipelined-MIPS-Processor-

Built a 5-stage pipelined MIPS processor in Verilog. The MIPS processor was developed using the synthesizable subset of Verilog, and the processor executed C programs compiled using GNU GCC. The input to the processor thus were the compiled SREC files which were parsed using a srec parser and fed into the processor.

Interactive-Programming-in-Python

Interactive Programming in Python

nengo

A Python library for creating and simulating large-scale brain models

Nengo2-Tutorials

Tutorials for 'How to Build a Brain Book'

test

s72sharm/nengo

A Python library for creating and simulating large-scale brain models

s72sharm/Nengo2-Tutorials

Tutorials for 'How to Build a Brain Book'

s72sharm/Interactive-Programming-in-Python

Interactive Programming in Python

s72sharm/5-Stage-Pipelined-MIPS-Processor

http://sugandhasharma.weebly.com/computer-architecture--digital-vlsi.html

s72sharm/5-stage-Pipelined-MIPS-Processor-

Built a 5-stage pipelined MIPS processor in Verilog. The MIPS processor was developed using the synthesizable subset of Verilog, and the processor executed C programs compiled using GNU GCC. The input to the processor thus were the compiled SREC files which were parsed using a srec parser and fed into the processor.

s72sharm/test