Pinned Repositories
azadi
[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core.
caravel_azadi_soc
https://caravel-user-project.readthedocs.io
aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
azadi-1
Azadi is an SoC with 32 bit RISC-V CPU core.
azadi-new
Azadi after tapeout
azadi-v3
azadi-verify
This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.
Azadi_II
https://caravel-user-project.readthedocs.io
RISCV-32I-chisel-version
tcam
sajjadahmed677's Repositories
sajjadahmed677/RISCV-32I-chisel-version
sajjadahmed677/tcam
sajjadahmed677/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
sajjadahmed677/azadi-1
Azadi is an SoC with 32 bit RISC-V CPU core.
sajjadahmed677/azadi-new
Azadi after tapeout
sajjadahmed677/azadi-v3
sajjadahmed677/azadi-verify
This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.
sajjadahmed677/Azadi_II
https://caravel-user-project.readthedocs.io
sajjadahmed677/azadi_sdk
sajjadahmed677/Book-on-MOS-stages
Book repository "Analysis and Design of Elementary MOS Amplifier Stages"
sajjadahmed677/caravel_ibtida_soc
sajjadahmed677/Chisel-Bootcamp
sajjadahmed677/Cores-SweRV-EL2
SweRV EL2 Core
sajjadahmed677/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
sajjadahmed677/Ibtida
A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
sajjadahmed677/openlane-example
sajjadahmed677/OpenTcam
sajjadahmed677/opentitan
OpenTitan: Open source silicon root of trust
sajjadahmed677/REST
sajjadahmed677/REST_II
sajjadahmed677/riscv-soc
sajjadahmed677/RV32I-chisel-version
sajjadahmed677/wishbone-bus
This repository contains wishbone bus components for master and slave devices