sakshamssy

sakshamssy's Stars

• kaxap/arl

  lists of most popular repositories for most favoured programming languages (according to StackOverflow)

  Language:Python2k7413187

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.6k159901.5k

• xiaop1/Verilog-Practice

  HDLBits website practices & solutions

  Language:Verilog700116178

• seldridge/verilog

  Repository for basic (and not so basic) Verilog blocks with high re-use potential

  Language:Verilog559533139

• dawsonjon/fpu

  synthesiseable ieee 754 floating point library in verilog

  Language:Verilog5482425148

• rajesh-s/computer-architecture-and-systems-resources

  A curated list of Computer Architecture and Systems resources

  47619253

• ridecore/ridecore

  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

  Language:Verilog33434465

• risclite/SuperScalar-RISCV-CPU

  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

  Language:SystemVerilog20414342

• Gowtham1729/Image-Processing

  Image Processing Toolbox in Verilog using Basys3 FPGA

  Language:VHDL1864137

• numato/samplecode

  This repository contains sample code for different Numato Lab products

  Language:C135270341

• Mericam/exposure-fusion

  Exposure Fusion in Matlab

  Language:Matlab1004145

• suisuisi/FPGAandImage

  image processing based FPGA

  Language:VHDL994027

• satu0king/Leetcode-Solutions

  My Submissions for over 1200 Leetcode Problems

  Language:C++832023

• damdoy/fpga_image_processing

  IP operations in verilog (simulation and implementation on ice40)

  Language:Verilog543015

• ivanvig/2dconv-FPGA

  A 2D convolution hardware implementation written in Verilog

  Language:Verilog444116

• aravindskrishnan/Retinex-Image-Enhancement

  Practical Implementation of Single Scale Retinex and Multiscale Retinex Algorithm in Python 3

  Language:Python412110

• MicrochipTech/fpga-hls-examples

  Open-Source HLS Examples for Microchip FPGAs

  Language:C391017

• arpesenti/exposure_fusion

  Python implementation of exposure fusion of multiple images

  Language:Python31315

• sh-vlad/FPGA_rtime_HDR_video

  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.

  Language:Verilog3132515

• fthaler/rawhdr

  A simple HDR image merger that converts multiple RAW files into a single HDR image.

  Language:Python30141

• tharunchitipolu/sobel-edge-detector

  Sobel is first order or gradient based edge operator for images and it is implemented using verilog.

  Language:Verilog14204

• ChienKaiMa/HDR-Imaging-with-FPGA

  High Dynamic Range imaging with Altera DE2-115.

  Language:SystemVerilog13111

• areberoto/Image-Conv-VHDL

  Implementation of a 2D Convolution Filter using VHDL for FPGAs.

  Language:VHDL12103

• MicrochipTech/fpga-hls-libraries

  Language:C8502

• XAli-SHX/Implementation-of-an-Edge-Detection-Filter-Using-the-Avalon-Interface

  Implementation of an Edge Detection Filter Using the Avalon Interface

  Language:Verilog4100

• 4mbilal/XilFPGAdev

  Language:VHDL3100

• Lakshani97/Digital-Image-Processing-Codes

  Codes for image pre-processing

  Language:C++3100

• nawalmunif/Image-Processing-on-FPGA

  An efficient FPGA-based design and implementation of image processing algorithm is presented using verilog hardware description language on Xilinx Vivado.

  3100

• adithi-su/fractional-phase-locked-loop

  Language:Verilog1101

• andreypapushin/FPGA_rtime_HDR_video

  1