sammy17's Stars
Krishnaps/Gem5-PCI-Express
Gem5 with PCI Express integrated.
darchr/novoverse
A set of configurations to model Arm's N1 cores.
architecture-research-group/gem5-dpdk-setup
This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
ufrisk/pcileech
Direct Memory Access (DMA) Attack Software
zero-day-labs/riscv-iommu-demo
RISC-V IOMMU Demo (Linux & Bao)
zero-day-labs/riscv-iommu
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
IPADS-DuVisor/DuVisor
riscv-non-isa/riscv-iommu
RISC-V IOMMU Specification
mysoreanoop/mlfuzz
vithurson/linux_compile
RPTU-EIS/upec-boom-verification-suite
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
compsec-snu/difuzz-rtl
cispa/osiris
Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
antmicro/cocotb-verilator-build
riscv-non-isa/riscv-asm-manual
RISC-V Assembly Programmer's Manual
Konin-Sensei/CNN-in-C
Convolutional Neural Network in C
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
nvdla/hw
RTL, Cmodel, and testbench for NVDLA
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
UniversityOfMoratuwa/RISCV
riscvarchive/riscv-linux
RISC-V Linux Port
lankas/SqueezeNet