A Rust embedded HAL crate for LiteX cores. It contains basic HAL traits for GPIO, UART, SPI, and delay.
More info and instructions on my blog and example project in this repo
The repository also contains an example that you can run on Verilator using litex_sim
.
The following dependencies are required to generate Rust code for peripherals (also called Peripheral Access Crate or PAC) and build the example for it.
Our example use VexRiscv, so to be able to compile them you need to add riscv32i-unknown-none-elf
target for Rust.
rustup target add riscv32i-unknown-none-elf
For LiteX scripts.
- ArchLinux:
sudo pacman -S python
- Ubuntu:
sudo apt install python3
- Universal LiteX script
To build cores and optionally simulate it using verilator.
The following dependencies are required if you want to run the example on litex_sim
.
To compile VexRiscv soft core. RISCV 64 can also build RISCV 32.
- ArchLinux:
sudo pacman -S riscv64-elf-gcc
- Ubuntu:
sudo apt install gcc-riscv64-unknown-elf
Simulator to run simulation.
- ArchLinux:
sudo pacman -S verilator
- Ubuntu:
sudo apt install verilator
LLVM tools, needed to convert the example from ELF to BIN.
rustup component add llvm-tools-preview
Rust task runner and build tool, needed to automate simulation.
- Cargo:
cargo install --no-default-features cargo-make
- ArchLinux (from AUR):
paru -S cargo-make
Cargo subcommands to invoke the LLVM tools, needed to convert the example from ELF to BIN.
- Cargo:
cargo install cargo-binutils
- ArchLinux (from AUR):
paru -S cargo-binutils
To run the simulation execute the following command:
cargo make simulate --example counter
You can pass additional Cargo flags such as --release
at the end of the simulation command.