/vhdl-multi-cycle-pipelined-calculator

My multi-cycle pipelined 8-bit calculator that I designed in VHDL for CPEG324: Computer Systems Design. I used GHDL and GTKWave to simulate my designs.

Primary LanguageVHDL

Lab 2: VHDL 8-bit Calculator

CPEG 324

Sean Krail

The design of this single-cycle calculator roughly follows the simple, single-cycle MIPS processor shown in this image, including the naming of components:

Image of the simple, single-cycle MIPS processor

Install GHDL 0.31 (may not be necessary, GHDL 0.29 should be fine... maybe)

sudo add-apt-repository ppa:pgavin/ghdl
sudo apt update
sudo apt install ghdl

Run test benches

  1. Enter make directory: cd make

  2. Remove current test bench binaries (may not be necessary): make clean

  3. Make test bench binaries a. Make all test bench binaries make b. Make a specific test bench binary make add2 make alu make and2 make calculator make control_unit make full_adder make half_adder make mux2 make or2 make register_file make sign_extend make xor2 make debug_aluregfile make debug_pc

  4. Execute a test bench binary ./add2_tb ./alu_tb ./and2_tb ./calculator_tb ./comparator2_tb ./control_unit_tb ./debug_aluregfile_tb ./debug_pc_tb ./full_adder_tb ./half_adder_tb ./mux2_tb ./or2_tb ./register_file_tb ./sign_extend_tb ./xor2_tb

Main test bench

  1. Enter make directory: cd make

  2. Remove current test bench binaries (may not be necessary): make clean

  3. Make calculator's test bench binary Make all or make calculator (they are equivalent) make make calculator

  4. Execute the test bench binary ./calculator_tb

  5. Create a GHW Waveform for GTKWave ./calculator_tb --wave=../gtkwave/pipelined.ghw

Features (definitely not bugs)

  • We print every clock cycle.
  • Overflow and underflow flags are set accordingly internally inside of the calculator, but our calculator never does anything about it.
  • Register file does reads just after (not on!) the rising_edge of clock.