Pinned Repositories
AIEplace
Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.
Annealing_Slicing_Layout
Use Simulated Annealing heuristic to obtain layouts for standard cell layouts
Annealing_Standard_Cell
Perform Simulated Annealing heuristic on a standard cell layout.
Channel_Routing
Algorithms which solve the channel routing and switchbox routing physical design problems.
DREAMPlace
Deep learning toolkit-enabled VLSI placement
DSE
Scripts to perform Design Space Exploration (DSE) using CyberWorkBench High-Level Synthesis tool
FM_Partitioning
Program which implements Fiduccia–Mattheyses partitioning algorithm
ISPD_2020
Code for the International Symposium of Physical Design (ISPD) 2020 Contest Objective is to provide heuristic solutions for Cerebras' Wafer Scale Engine (WSE)
mlir-aie
An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.
MSDAP
Verilog project to implement an ASIC chip from specification to tape out. Performs audio filtering, known as the Mini Stereo Digital Audio Processor (MSDAP)
searsm8's Repositories
searsm8/AIEplace
Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.
searsm8/Channel_Routing
Algorithms which solve the channel routing and switchbox routing physical design problems.
searsm8/MSDAP
Verilog project to implement an ASIC chip from specification to tape out. Performs audio filtering, known as the Mini Stereo Digital Audio Processor (MSDAP)
searsm8/FM_Partitioning
Program which implements Fiduccia–Mattheyses partitioning algorithm
searsm8/ISPD_2020
Code for the International Symposium of Physical Design (ISPD) 2020 Contest Objective is to provide heuristic solutions for Cerebras' Wafer Scale Engine (WSE)
searsm8/Annealing_Standard_Cell
Perform Simulated Annealing heuristic on a standard cell layout.
searsm8/DSE
Scripts to perform Design Space Exploration (DSE) using CyberWorkBench High-Level Synthesis tool
searsm8/Annealing_Slicing_Layout
Use Simulated Annealing heuristic to obtain layouts for standard cell layouts
searsm8/DREAMPlace
Deep learning toolkit-enabled VLSI placement
searsm8/mlir-aie
An MLIR-based toolchain for Xilinx Versal AIEngine-based devices.
searsm8/LeNet
Simple implementation of LeNet using PyTorch
searsm8/mlir-hello
MLIR Sample dialect
searsm8/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
searsm8/phdlog
Day-to-day log files of my PhD research
searsm8/RePlAce
RePlAce global placement tool
searsm8/searsm8
Config files for my GitHub profile.
searsm8/verilog_modules
A collection of useful verilog modules
searsm8/Vitis-Tutorials
Vitis In-Depth Tutorials