TEST BENCH
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Sir, the test bench file has errors. Can you please send the updated file?
You need to provide more information. Which testbench file have errors? What errors are you seeing? When do you see the errors?
Are you talking about tb_aes.v in src/tb? In master branch? If that is the file, There are no errors. I can build and run the simulation. Those lines correspond to task calls. Tasks with no arguments does not need to have parens (and some tools complain when they do.)
What compiler/parser are you using when getting the errors? Please post more information, preferably logs from the tool.
When talking about a too many variables - are you talking about the aes core itself or the testbench?
No, there is no documentation etc complementing the core outside of the repo. The core is simple enough that it should be usable as is.
Ok. Good that you found the errors
Just to check - you undeerstand that this is a hardware implementation for FPGAs and ASICs, right? This means that it needs a clock (clk), and that the core will need to be operated in relation to the clock. Since you are looking at tb_aes.v, you use the core by reading and writing 32-bit words to the addresses specified. In general, in order to use the core you need to:
- Load the key to be used by writing to the key register words.
- Set the key length by writing to the config register.
- Initialize key expansion by writing a one to the init bit in the control register.
- Wait for the ready bit in the status register to be cleared and then to be set again. This means that the key expansion has been completed.
- Write the cleartext block to the block registers.
- Start block processing by writing a one to the next bit in the control register.
- Wait for the ready bit in the status register to be cleared and then to be set again. This means that the data block has been processed.
- Read out the ciphertext block from the result registers.
If you look at the testcases in tb_aes.v you will see that this flow is what is performed.
Note that this is an implementation of the FIPS-197 block cipher function. If you are going to use the AES core for any real messages you MUST use it in a block cipher mode of operation, for example as part of GCM, CCM. This core does not implement these modes. It is just the AES block cipher.
Due to your question and request I will probably clarify and update the README.md with a description like the one above on how to operate the code. But I will also close this issue.
No errors. So closing this.
Don't see any screenshot, neither here nor at the link. Please post the errors you see in text here.
Interesting paper and S-box technique you are implementing.