Input Text File
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May I know where to input text file in this series of Verilog codes?
Thank you.
Hi abifedun!
I will try to help you, but I'm not sure how to parse that question.
Please explain a bit better. What is it that you want to do?
I am currently conducting a simple project where it involves inputting data from the sensor into an AES encryption. I want to know how likely the .dat file can be input into the Verilog code you provided. Thank you.
Ok, I hope I don't insult you or anything - but have you understood what Verilog is?
The Verilog code is the source files, the description used by tools for FPGA and ASIC implementations to generate a hardware implementation. That is gates, registers, wires and ports. This is not SW code to be executed on a CPU.
If you are going to use this you need to have something (a CPU core, a microconteroller och a finite state machine) that takes your data (not a file, the data itself), divide it into 16 byte blocks and feed the blocks via the connections to the AES engine. For each block you need to pull the next() signal for a clock cycle to trigger processing. Before doing this you need to provide a key (128 or 256 bits) and pull init() for a cycle to trigger a key expansion. For each of these you need to observe the ready() signal to be asserted, signalling that the processing has been completed (for that block etc).
Also, note that this engine is the pure AES (FIPS 197) function. It does not implement a proper block cipher mode such as CBC, CTR, OCB etc. You need to implement the modes on top of the AES engine. This can often be done easily in SW. But they can also be implemented in HW as a wrapper around the core,.
The AES implementation provides two interfaces. aes_core.v provides wide interfaces that allows for high performance operations with the core as part of a design, for example in a HW implementation of modes. aes.v provides a simple, 32-bit interface suitable for low complexity integration with ARM, RISC-V MCUs and CPU cores.
Please explain, describe the system you have. Are you in fact doing hardware implementations?
Closing this.
If I want to implement a GUI interface where I can input text file in ModelSim. Can you guide me through this?
Sorry no. There are example testcases in src/tb/tb_aes_core.v or tb_aes.v that shows how to use the AES engine with blocks of data. That should be enough for you to use the core. But the GUI work is not someting I have worked with.
What file is that? As far as I know, there is no SystemVerilog (.sv) file called aesEnc.sv in the aes repository. I don't use SystemVerilog, and I would never use that name on a file.
As I explained. Look at the testbench in src/tb and write code (or a script) that takes your input and convert to a series of block cipher operations.