A 32 bit processor written in structural VerilogHDL in Quartus II. It supports 36 intructions and has a data memory of 128KB.
“memory.txt” and “instructions.txt” files are need in the simulation directory. Some test instructions are given ,it includes all the instructions.
There are 36 instructions 8 instruction is extra. The system is designed for 128 KB data memory all the wires are written according to that but I made the data byte array size 501 in the memory module otherwise it was very slow (my computer didn’t run it) to compile. Others remain the same. These are the instructions supported with some of their control signals.
Instruction Table| Ins. Name | Type | Opcode | Func. | MemWrite | MemRead | RegWrite | MemtoReg | RegDst | Branch |
| Xor | R | 00 0000 | 10 0110 | 0 | 0 | 1 | 0 | 1 | 0 |
| Xori | I | 00 1110 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Slt | R | 00 0000 | 10 1010 | 0 | 0 | 1 | 0 | 1 | 0 |
| Sltui | I | 00 1011 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Sltu | R | 00 0000 | 10 1011 | 0 | 0 | 1 | 0 | 1 | 0 |
| Slti | I | 00 1010 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Lw | I | 10 0011 | XX XXXX | 0 | 1 | 1 | 1 | 0 | 0 |
| Lh | I | 10 0001 | XX XXXX | 0 | 1 | 1 | 1 | 0 | 0 |
| Lb | I | 10 0000 | XX XXXX | 0 | 1 | 1 | 1 | 0 | 0 |
| Lui | I | 00 1111 | XX XXXX | 0 | 0 | 1 | X | 0 | 0 |
| Sw | I | 10 1011 | XX XXXX | 1 | 0 | 0 | X | 0 | 0 |
| Sb | I | 10 1000 | XX XXXX | 1 | 0 | 0 | X | 0 | 0 |
| sh | I | 10 1001 | XX XXXX | 1 | 0 | 0 | X | 0 | 0 |
| J | J | 00 0010 | XX XXXX | 0 | 0 | 0 | X | X | X |
| Jal | J | 00 0011 | XX XXXX | 0 | 0 | 0 | X | X | X |
| Jr | R | 00 0000 | 00 1000 | 0 | 0 | 0 | X | X | X |
| Beq | I | 00 0100 | XX XXXX | 0 | 0 | 0 | X | X | 1 |
| Bne | I | 00 0101 | XX XXXX | 0 | 0 | 0 | X | X | 1 |
| Add | R | 00 0000 | 10 0000 | 0 | 0 | 1 | 0 | 1 | 0 |
| Sub | R | 00 0000 | 10 0010 | 0 | 0 | 1 | 0 | 1 | 0 |
| And | R | 00 0000 | 10 0100 | 0 | 0 | 1 | 0 | 1 | 0 |
| Or | R | 00 0000 | 10 0101 | 0 | 0 | 1 | 0 | 1 | 0 |
| Sra | R | 00 0000 | 00 0011 | 0 | 0 | 1 | 0 | 1 | 0 |
| Srl | R | 00 0000 | 00 0010 | 0 | 0 | 1 | 0 | 1 | 0 |
| Sll | R | 00 0000 | 00 0000 | 0 | 0 | 1 | 0 | 1 | 0 |
| sllv | R | 00 0000 | 00 0100 | 0 | 0 | 1 | 0 | 1 | 0 |
| srlv | R | 00 0000 | 00 0110 | 0 | 0 | 1 | 0 | 1 | 0 |
| srav | R | 00 0000 | 00 0111 | 0 | 0 | 1 | 0 | 1 | 0 |
| Addi | I | 00 1000 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Addiu | I | 00 1001 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Andi | I | 00 1100 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| Ori | I | 00 1101 | XX XXXX | 0 | 0 | 1 | 0 | 0 | 0 |
| lbu | I | 10 0100 | XX XXXX | 0 | 1 | 1 | 1 | 0 | 0 |
| lhu | I | 10 0101 | XX XXXX | 0 | 1 | 1 | 1 | 0 | 0 |
| nor | R | 00 0000 | 10 0111 | 0 | 0 | 1 | 0 | 1 | 0 |
| subu | R | 00 0000 | 10 0011 | 0 | 0 | 1 | 0 | 1 | 0 |