Check SPI configuration of DSP clock generator
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The CDCE62002 should be programmed with the following configuration:
REGISTERS
0 55200080
1 8389A061
2 00000002
The result should be a 150MHz LVDS clock signal to the DSP.
Using 50MHz DDR3 / 100MHz CORECLK for GEL compatibility with EVM6657. Current params are 55D00080 / 8383E001. However, PLL lock isn't possible with those params — maybe feedback bandwidth too narrow?
Current params are 54200080 / B7870061. These are good enough for the DSP to work properly, but the PLL doesn't lock if 1V8 is present.
Daniel noticed that temporarily shorting the 3V3 rail (which resets everything) results in the PLL locking. Check sequencing parameters to see if timing of SPI programming results in lock.
The latest version of the CDCE62002 datasheet suggests register bit 13 (SPI word bit 17) of register 2 should be set in order to allow VCO recalibration. We hadn't been setting that previously, so this could be the problem.
Working with:
54200080
b7870061
61023bf2
(The last register is programmed as 61023bf2, 60023bf2, 61023bf2 to force a VCO recalibration.)