Pinned Repositories
cnn
基于Java实现CNN，并附MNIST和语音（MFCC特征）性别识别示例。
ConvNN_FPGA_Accelerator
Convolutional-Neural-Network-hardware-using-Verilog
A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).
DES
FPGA-CNN
FPGA implementation of Cellular Neural Network (CNN)
FPGA-Imaging-Library
An open source library for image processing on FPGA.
FPGA_Based_CNN
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
hdl
HDL libraries and projects
leetcode
sh1neon.github.io
sh1neon's Repositories
sh1neon/cnn
基于Java实现CNN，并附MNIST和语音（MFCC特征）性别识别示例。
sh1neon/ConvNN_FPGA_Accelerator
sh1neon/Convolutional-Neural-Network-hardware-using-Verilog
A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).
sh1neon/DES
sh1neon/FPGA-CNN
FPGA implementation of Cellular Neural Network (CNN)
sh1neon/FPGA-Imaging-Library
An open source library for image processing on FPGA.
sh1neon/FPGA_Based_CNN
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
sh1neon/hdl
HDL libraries and projects
sh1neon/leetcode
sh1neon/sh1neon.github.io
sh1neon/oh
Silicon proven Verilog library for IC and FPGA designers
sh1neon/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
sh1neon/VOC2007