shady831213/terminus_cosim

Terminus + verilog cosim env to show the cosim power of terminus

terminus_cosim

This project is a cosim sulotion of ISA + verilog. It shows terminus is friendly to be integrated into HDL simulation enviroment. It also provides framework to support communication between cpu cores, ISA or real RTL cpu cores, and the host machine though mailbox_rs and vfw_rs.Besides, vfw_rs provides testcase framework with some useful services, and it supports both rust testcases and c testcases.

Main Dependencies

• HDL Simulator: verilator.
• Toolchain:
  • Rust nightly toolchain with target riscv32imac-unknown-none-elf
  • bindgen dependencis
  • riscv-gnu-toolchain if you want C testcase supporting.
  • cargo-binutils

Getting Start

// Suppose all dependencies are ready
git clone https://github.com/shady831213/terminus_cosim
cd terminus_cosim
git submodule update --init
./run.sh [hello_world|hello_world_c|trap|wait_event|svcall]

Then you should get:

About other EDA tools

Other EDA tools, such as xrun, are also supported, but you need modify some DPI method to adapt to them.