/AUCOHL_UART

A more complete UART

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AUCOHL_UART

A more complete UART

The Interface

Diagram

Parameters

Generic name Value Description
MDW 9 Maximum data word width
FAW 4 FIFO Address Width; $FIFO\ Depth=2^{FAW}$
SC 8 Number of Samples
GFLEN 8 Input Glitch Filter Length

Ports

Port name Direction Type Description
clk input wire
rst_n input wire
prescaler input wire [15:0]
en input wire
tx_en input wire
rx_en input wire
rd input wire
wr input wire
wdata input wire [MDW-1:0]
data_size input wire [3:0]
stop_bits_count input wire
parity_type input wire [2:0]
txfifotr input wire [3:0]
rxfifotr input wire [3:0]
match_data input wire [MDW-1:0]
timeout_bits input wire [5:0]
loopback_en input wire
glitch_filter_en input wire
tx_empty output wire
tx_full output wire
tx_level output wire [FAW-1:0]
tx_level_below output wire
rdata output wire [MDW-1:0]
rx_empty output wire
rx_full output wire
rx_level output wire [FAW-1:0]
rx_level_above output wire
break_flag output wire
match_flag output wire
frame_error_flag output wire
parity_error_flag output wire
overrun_flag output wire
timeout_flag output wire
rx input wire
tx output wire

I/O Registers

This section covers the I/O register definitions which are the same for the provided bus wrappers.

Name Offset Reset Value Access Mode Description
RXDATA 0000 0x00000000 r RX Data register; the interface to the Receive FIFO.
TXDATA 0004 0x00000000 w TX Data register; ; the interface to the Receive FIFO.
PR 000c 0x00000000 w The Prescaler register; used to determine the baud rate. $Baud\ Rate = (Clock\ freq.)/((PR+1)\times16)$.
CTRL 0008 0x00000000 w UART Control Register
CFG 0010 0x00003F08 w UART Configuration Register
FIFOCTRL 0014 0x00000000 w FIFO Control Register
FIFOS 0018 0x00000000 r FIFO Status Register
MATCH 001c 0x00000000 w Match Register
IM 0f00 0x00000000 w Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details
RIS 0f08 0x00000000 w Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details
MIS 0f04 0x00000000 w Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details
IC 0f0c 0x00000000 w Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details

RX Data register; the interface to the Receive FIFO. [Offset: 0x0, mode: r]

RX Data register; the interface to the Receive FIFO.

TX Data register; ; the interface to the Receive FIFO. [Offset: 0x4, mode: w]

TX Data register; ; the interface to the Receive FIFO.

The Prescaler register; used to determine the baud rate. $baud_rate = clock_freq/((PR+1)*16)$. [Offset: 0xc, mode: w]

The Prescaler register; used to determine the baud rate. $baud_rate = clock_freq/((PR+1)*16)$.

UART Control Register [Offset: 0x8, mode: w]

UART Control Register

bit field name width description
0 en 1 UART enable
1 txen 1 UART Transmitter enable
2 rxen 1 UART Receiver enable
3 lpen 1 Loopback (connect RX and TX pins together) enable
4 gfen 1 UART Glitch Filer on RX enable

UART Configuration Register [Offset: 0x10, mode: w]

UART Configuration Register

bit field name width description
0 wlen 4 Data word length: 5-9 bits
4 stp2 1 Two Stop Bits Select
5 parity 3 Parity Type: 000: None, 001: odd, 010: even, 100: Sticky 0, 101: Sticky 1
8 timeout 6 Receiver Timeout measured in number of bits

FIFO Control Register [Offset: 0x14, mode: w]

FIFO Control Register

bit field name width description
0 TXLT 4 Transmit FIFO Level Threshold
8 RXLT 4 Receive FIFO Level Threshold

FIFO Status Register [Offset: 0x18, mode: r]

FIFO Status Register

bit field name width description
0 RXL 4 Receive FIFO Level
8 TXL 4 Transmit FIFO Level

Match Register [Offset: 0x1c, mode: w]

Match Register

Interrupt Flags

The following are the bit definitions for the interrupt registers: IM, RIS, MIS, and IC.

Bit Flag Width Description
0 TXE 1 Transmit FIFO is Empty.
1 RXF 1 Receive FIFO is Full.
2 TXB 1 Transmit FIFO level is Below Threshold.
3 RXA 1 Receive FIFO level is Above Threshold.
4 BRK 1 Line Break; 13 consecutive 0's have been detected on the line.
5 MATCH 1 Match; the receive data matches the MATCH register.
6 FE 1 Framing Error; the receiver does not see a "stop" bit at the expected "stop" bit time.
7 PRE 1 Parity Error; the receiver calculated parity does not match the received one.
8 OR 1 Overrun; data has been received but the RX FIFO is full.
9 RTO 1 Receiver Timeout; no data has been received for the time of a specified number of bits.