- x8 PLL Clock Multiplier: x8 Clock Multiplier.
- Phase Locked Loop (PLL): A PLL is a negative feedback control system that generates an output clock signal whose phase is related to the phase of an input clock signal. A PLL can be used to multiply a low-frequency external reference clock (generated by a crystal oscillator) up to the operating frequency of the processor.
- Analog Comparator: A 3.3V analog comparator.
- Analog Comparator: CMOS Rail-To-Rail Comparator
- Analog MUX, Switch and Comparator: Collection of analog and mixed signal test circuits.
- Potentiometric Digital to Analog Converter (DAC): A 10-bit potentiometric DAC with 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference.
- Potentiometric Digital to Analog Converter (DAC): Another 10-bit potentiometric DAC.
- Sigma-Delta AUdio DAC: Delta-sigma audio DAC (16b, 48kHz).
- 8-bit SAR ADC: This submission consists of a updated 8-bit SAR-ADC, basic analog support circuitry, such as bandgap reference, bias network, voltage regulators and a clk generator. Earlier Version.
- VCO ADC: Voltage COntrolled Oscillator Based Analog to Digital Converter
- 1.8V LDO: 100mA 1.8V Low Dropout Voltage Regulator.
- 1.8V Buck Converter: A current mode buck converter on the SKY130 PDK.
- LDO, Power Swicth and 1.2V BGR: These IPs can be integrated to construct a 1.2V LDO.
- OpAmp: 2-stage, frequency-compensated OpAmp
- OpAmp: General-Purpose OpAmp.
- 2-stage OpAmp: A Two Stage CMOS Operational Amplifier
- OpAmp: OpAmp by one of Zero to ASIC users.
- DPGA: Digitally Programmable Gain Amplifier.
- SerDes: Digitally synthesizable architecture for SerDes
- HyperRAM Controller: Wishbone HyperRAM controller.
- no2USB: a USB Full-Speed SIU using only CMOS IOs.
- USB 2.0 CDC Core: Verilog implementation of the Full Speed (12Mbit/s) USB communications device class (or USB CDC class). It implements the Abstract Control Model (ACM) subclass.