/Caravel_N5_SoC

Primary LanguageVerilogApache License 2.0Apache-2.0

Caravel_N5_SoC

The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v and this.

GDS View