A set of HDL modules and header files to accelerate the process of constructing AMBA (AHB-lite and APB) based SoCs:
rtl/AB_APN_BRIDGE.v: AHB-Lite to APB Bridge with programmable clock divider.rtl/AHB_DMAC_1CH.v: A single channel DMA controller with AHB-Lite Master and Slave Interfaces.rtl/AHB_FLASH_CTRL.v: AHB-Lite QSPI FLash Controller with Read-Only Direct Mapped Cache.rtl/AHB_FLASH_WRITER.v: AHB-Lite Flash Writer (Slave).rtl/AHB_MUX_2M1S.v: AHB-Lite 2x1 Master multiplexor (2 modes of operation).rtl/AHB_UART_MASTER.v: UART to AHB-Lite (Master) Bridge.rtl/FIFO.v: A parametrized FIFO.
/dv: Verification Testbenches and the associates include and Make files./include: Utility include files for constructing AHB and APB based sub-systems./examples: Examples to demonstrate the usage of the AHB/APB nclude files.
| IP | Description | Status | Testbench |
|---|---|---|---|
| AHB_SRAM | AHB SRAM Controller | 98% | AHB_SRAM_TB.v |
| AHB_UART_MASTER | A UART that can act as AHB master | 90% | AHB_UART_MASTER.v |
| AHB_FLASH_WRITER | AHB Slave used to program the QSI Flash | 95% | AHB_UART_MASTER.v |
| AHB_FLASH_CTRL | AHB QSI Flash Controller with a small DM cache (read only) | 95% | n/a |
| AHB_APB_BRIDGE | AHB/APB Bridge | 95% | example_4_tb.v |
| AHB_MUX_2M1S | Dual mode AHB masters multiplexor | 95% | n/a |