shantanu5092

Bidding-arbiter

Designed a bidding arbiter for granting bus access to the selected master

Implement-and-Analyze-different-types-of-64-bit-adders

Designed and synthesized different types of 64-bit adders

Network-on-Chip-NOC-

The Network on a chip is a pair of low pin count uni-directional bus.

NOC-Bus-master-

This module adds bus master capabilities to the NOC interface

Python-script-to-search-for-a-file-in-OS-and-then-replace-the-content

This is a Python script to search for a particular file based on the user input in the operating system and replacing the content of the file with the user input.

Python-script-to-automate-the-task-of-timing-analysis-for-RTL-designs-Timing-closure-

Python script to check and fix timing violation for the RTL design in order to meet the timing requirements

APB-master-slave-verification-IP-using-UVM

Developing an APB master/slave verification IP using UVM

Box-Muller-Tansform-Floating-Point-Random-number-distribution-

This is a synthesizable block that implements the Box-Muller transform to convert two random number to an approximation of a Gaussian random number distribution.

Cyclic-Redundancy-Check-block-CRC-

This is a synthesizable CRC block coded in System Verilog as per the specification given in the NXP document.

Verification-of-an-8-bit-ALU-module

Performed verification of an 8-bit arithmetic logic module using constraint random testing and UVM libraries.

shantanu5092/Capture

shantanu5092/APB-master-slave-verification-IP-using-UVM

Developing an APB master/slave verification IP using UVM

shantanu5092/FGPA-based-hardware-accelerator-for-CNN

The project aims to develop a hardware accelerator for CNN.

shantanu5092/Verification-of-an-8-bit-ALU-module

Performed verification of an 8-bit arithmetic logic module using constraint random testing and UVM libraries.

shantanu5092/Python-script-to-automate-tests

Developed a Python script to automate the task of testing multiple FIFO DUT's together using UVM

shantanu5092/Bluetooth-Android-Application

Developed an android application for communication between embedded board over bluetooth.

shantanu5092/Bidding-arbiter

Designed a bidding arbiter for granting bus access to the selected master

shantanu5092/Python-script-to-automate-the-task-of-timing-analysis-for-RTL-designs-Timing-closure-

Python script to check and fix timing violation for the RTL design in order to meet the timing requirements

shantanu5092/Python-script-to-search-for-a-file-in-OS-and-then-replace-the-content

This is a Python script to search for a particular file based on the user input in the operating system and replacing the content of the file with the user input.

shantanu5092/NOC-Bus-master-

This module adds bus master capabilities to the NOC interface

shantanu5092/Network-on-Chip-NOC-

The Network on a chip is a pair of low pin count uni-directional bus.

shantanu5092/Implement-and-Analyze-different-types-of-64-bit-adders

Designed and synthesized different types of 64-bit adders

shantanu5092/Box-Muller-Tansform-Floating-Point-Random-number-distribution-

This is a synthesizable block that implements the Box-Muller transform to convert two random number to an approximation of a Gaussian random number distribution.

shantanu5092/Cyclic-Redundancy-Check-block-CRC-

This is a synthesizable CRC block coded in System Verilog as per the specification given in the NXP document.