shanyinshuiyue

Pinned Repositories

100-Days-Of-ML-Code
100-Days-Of-ML-Code中文版
Language:Jupyter Notebook0 0 00
100-gcc-tips
A collection of gcc tips. 100 maybe just mean many here.
Language:Go0 0 00
2dconv-FPGA
A 2D convolution hardware implementation written in Verilog
Language:Verilog0 0 00
ad936x-filter-wizard
MATLAB-based FIR filter design
Language:MATLAB0 0 00
ad937x-filter-wizard
MATLAB-based FIR filter and profile designer
Language:C0 0 00
adi_adrv9371_zc706
adi's adrv9371 example integration with DVB-S2 IP
Language:Verilog0 0 00
aib-phy-hardware
Advanced Interface Bus (AIB) die-to-die hardware open source
Language:Verilog00
BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Language:SystemVerilog1 0 00
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Language:Python1 0 00

shanyinshuiyue's Repositories

shanyinshuiyue/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Language:Python1 0 00
shanyinshuiyue/Approx_Mul_FPGA
Language:Verilog0 0 00
shanyinshuiyue/antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
Language:SystemVerilog0 0
shanyinshuiyue/basil
A data acquisition framework in Python and Verilog.
Language:Python0 0
shanyinshuiyue/bfasst
Tools for FPGA Assurance Flows
Language:VHDL0 0
shanyinshuiyue/bladeRF
bladeRF USB 3.0 Superspeed Software Defined Radio Source Code
shanyinshuiyue/en_cl_fix
VHDL Fixed Point Library with Bit-True MATLAB Models
Language:VHDL
shanyinshuiyue/flames
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
shanyinshuiyue/galapagos
Language:VHDL0 0
shanyinshuiyue/hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
shanyinshuiyue/HyperRAM
Portable HyperRAM controller
Language:VHDL0 0
shanyinshuiyue/iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Language:SystemVerilog0 0
shanyinshuiyue/liquid-dsp
digital signal processing library for software-defined radios
Language:C0 0
shanyinshuiyue/Multiported-RAM
Modular Multi-ported SRAM-based Memory
shanyinshuiyue/nanoMODBUS
A compact MODBUS RTU/TCP C library for embedded/microcontrollers
Language:C0 0
shanyinshuiyue/Pake
🤱🏻 Turn any webpage into a desktop app with Rust. 🤱🏻 利用 Rust 轻松构建轻量级多端桌面应用
Language:Rust0 0
shanyinshuiyue/psi_common
Common elements for FPGA Design (FIFOs, RAMs, etc.)
Language:VHDL0 0
shanyinshuiyue/R76Firmware
DT5560SE firmwares and associated programs primarily designed for R76 for CDMS at UMN
Language:VHDL0 0
shanyinshuiyue/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
Language:C0 0
shanyinshuiyue/sdr-psk-fpga
Dual-Mode PSK Transceiver on SDR With FPGA
shanyinshuiyue/stb
stb single-file public domain libraries for C/C++
Language:C0 0
shanyinshuiyue/surf
A huge VHDL library for FPGA development
Language:VHDL
shanyinshuiyue/udmabuf
User space mappable dma buffer device driver for Linux.
Language:C0 0
shanyinshuiyue/usdr-fpga
FPGA for uSDR
Language:Verilog0 0
shanyinshuiyue/uthash
C macros for hash tables and more
shanyinshuiyue/verilog_library
Library of handy verilog modules
Language:Verilog0 0
shanyinshuiyue/Verilog_Module
自己使用到的verilog_module
Language:Verilog0 0
shanyinshuiyue/vu13p
国产VU13P加速卡资料
Language:C0 0
shanyinshuiyue/xuppl4_abm_gen
ABM-generator implemented on XUP-PL4
shanyinshuiyue/zedboard_adrv9002_project
Implementation of an IEEE 802.11p PHY realitime receiver in VHDL on ZedBoard and ADRV9002. Master's thesis at CTU in Prague FEE.
Language:VHDL0 0